Semiconductor memories are often employed in systems with a need to transfer blocks of information from one location or peripheral to another thereby serving as temporary storage locations. Any limitations of such memories effect system performance in terms of speed and efficiency. For example, throughput of systems employing prior art memory is substantially reduced when the system's peripheral or utilization devices are restricted in accessing blocks of information from the memory concurrently. Discussion of prior art memory architectures in specific applications will aid in understanding reasons for the reduction of system performance due to memory design limitations.
FIG. 1 shows an application specific memory according to U.S. Pat. No. 4,541,075, by Dill et al. where the memory is a semiconductor or IC device. Dill employs a main memory array coupled to a port and arranged in rows and columns, each row having the same number of n-bit wide words. Additionally incorporated in the semiconductor memory is a row buffer register which can transfer rows of data between the main memory and a second Input/Output port for accessing the row buffer register in either serial or parallel mode. A limitation of the memory device described in Dill is that only one utilization device can independently use the second I/O port. Furthermore, writing of a selected n-bit wide word sometimes referred to as partial write or masked write, from the row buffer register to a row of the main memory can not be achieved by the memory device proposed by Dill et al. In this memory device the partial write can be emulated by "memory row read modify write" operation which includes the steps of: transferring the row from the main memory to the row buffer register, modifying the row buffer register through the second I/O port, and transferring the row buffer register back to the row of the main memory. This "memory row read modify write" operation assumes that the data of the same row in the main memory was not changed between the read and write back. Note that data corruption will occur if during a "memory row read modify write" operation, part of the data in the main memory row was modified through the first I/O port (the port coupled to the main memory). This is a general limitation of the prior art and will be discussed in more detail below.
A major limitation in providing access by multiple independent utilization devices through a dedicated port per utilization device to a dedicated row buffer register is that concurrent write to the same row of the main memory by two or more utilization devices is not possible because partial write is not supported. FIG. 2 shows an extension of the memory device taught by Dill et al. including yet a third I/O port for accessing a second row buffer independent of the first row buffer for use by a second utilization device. FIG. 3 shows two blocks in the main memory wherein the tail end of block 1 and beginning of block 2 are in the same row of the main memory (row 2). Consider an application in which the first utilization device is using the first row buffer register through the second I/O port and a second utilization device is using the second row buffer register through the third I/O port, and furthermore utilization device 1 is accessing block 1, and utilization device 2 is accessing block 2. Now consider the following sequence of operations in this example: utilization device 1 reads row 2 of the memory into the first row buffer register and starts modifying the first row buffer register through the second I/0 port, utilization device 2 reads the same row of memory into the second row buffer register and starts modifying the second row buffer register through the third I/0 port. Utilization device 1 completes modifying the beginning of the row buffer register which is part of block 1 and writes it back to the row of the memory, utilization device 2 completes modifying the tail end of the second row buffer register which is part of the block 2 and writes it back to the row of the memory. It should be apparent that the last operation will then overwrite the data of block 1 which was modified by utilization device 1, and causes data corruption.
While problems as discussed above such as data corruption, etc. can be avoided, this is only achieved at the cost of limiting memory utilization by requiring that either the size of the block of data to be a multiple of a row size (which may not always be possible) or waste portions of the memory.
Furthermore, multiple parallel-by-bit I/O ports each coupled to a utilization device increases the number of pins of the memory device package, which increases cost of the memory device.
The semiconductor memory as taught by the present invention resolves limitations of prior art memories to achieve higher system performance. An application of the present invention as taught in a related patent application with a title of Semiconductor Memory Device for Mass Storage Block Access applications and Ser. No. 08/421,652, would be in disc drives where there is a need for a cost effective high performance multiport memory for allowing independent accesses to the memory by multiple peripherals or utilization devices.